Semiconductor integrated circuit device

ABSTRACT

A semiconductor integrated circuit device of a low power consumption capable of performing under a low voltage has an array section  21  in which only low threshold voltage MOS FETs are formed, and areas other than the array section  21  in which high threshold voltage MOS FETs whose threshold voltage is higher than that of each low threshold voltage MOS FET formed in the array section are formed.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor integratedcircuit device of a low electric power consumption type.

[0003] 2. Description of the Prior Art

[0004]FIG. 1 is a circuit diagram showing the configuration of a circuitcapable of performing under a low electric voltage as a semiconductorintegrated circuit device that will be used for explanation of preferredembodiments according to the present invention and followingconventional examples. The diagram of this circuit capable of performingunder the low voltage shown in FIG. 1 was also disclosed in the patentdocument of Japanese patent laid open publication number JP-A-7/212218as a conventional semiconductor integrated circuit device.

[0005] The circuit capable of performing under a low electrical voltageas a semiconductor integrated circuit device shown in FIG. 1 comprisesmulti-threshold complementary metal oxide semiconductors (hereinafteralso referred to as MT CMOS).

[0006] In FIG. 1, the reference number 1 designates a two-input NANDgate. Each of the reference numbers 2 and 3 denotes a p channel typemetal oxide semiconductor field effect transistor (hereinafter referredto as a p MOS FET). Each of the reference numbers 4 and 5 indicates a nchannel type metal oxide semiconductor field effect transistors(hereinafter referred to as a n channel MOS FET). In the circuit shownin FIG. 1, the absolute value of the threshold voltage of this p MOS FETis set to a low value and the absolute value of the threshold voltage ofthis n MOS FET is set to a high value. The reference number 6 designatesa power source of a predetermined voltage, 7 denotes a ground powersource. The reference number 8 indicates a p channel MOS FET connectedbetween the power source 6 and a power source line 12 as a hypotheticalpower source line. This p channel MOS FET 8 becomes active when a gateterminal of the P channel MOS FET 8 receives a control signal 9. Thereference number 10 indicates a n channel MOS FET connected between theground 7 and a ground line 13 that is a hypothetical ground line. This nchannel MOS FET 10 becomes active when a gate terminal of the n channelMOS FET 10 receives a control signal 11. In this circuit shown in FIG.1, it is formed so that the absolute values of the threshold voltages ofthe p channel MOS FET 8 and the n channel MOS FET 10 are higher than theabsolute values of the threshold voltages of the p channel MOS FETs 2and 3 and the n channel MOS FETs 4 and 5 forming the two-input NAND gate1, respectively.

[0007]FIG. 2 is a conventional layout pattern of a memory cell array ina conventional semiconductor integrated circuit device that wasdisclosed in the patent document of Japanese patent laid openpublication number JP-A-8/18021. In FIG. 2, the reference number 210indicates an array section in which a plurality of MOS FETs are arrangedin an array form. The reference numbers 220, 230, 240, and 250 denoteinput/output circuit forming sections located in a peripheral section ofthe array section 210, in which input/output circuits are formed. Thereference number 260 designates a region in which MOS FETs, each havinga high threshold voltage, are formed in the array section 210. Further,the reference number 270 designates a region in which MOS FETS, eachhaving a low threshold voltage, are formed in the array section 210.

[0008] Next, a description will be given of the operation of theconventional circuit capable of performing under a low supply voltage asthe conventional semiconductor integrated circuit device shown in FIG. 2

[0009] In recent years, there have been significant advancements oftechnology in portable devices such as mobile telephone devices and theportable devices are widely used in the world. Accordingly, it must berequired to operate those portable devices under a lower power voltagein order to maintain the voltage of a battery as long as possible. Toreduce the operational voltage used in the portable devices is aneffective method to reduce the power consumption of the portable devicesas small as possible. Because the power consumption is obtained bymultiple of a voltage value and a current value, it is possible toreduce both the voltage value and the current value by reducing theoperational voltage of the devices. In general, this method causes toobtain a greatly effect to reduce the power consumption of the devices.However, a MOS FET forming a semiconductor integrated circuit has adrawback in which the operation speed of the MOS FET becomes lowaccording to reducing of the op rational voltage. This characteristic ofthe MOS FET is based on that its threshold voltage is not reduced inproportion to the reducing of the voltage value of the power source. Thereason is that the magnitude of a leak current under an off state (aninactive state) of the MOS FET is increased when the threshold voltageof the MOS FET is decreased, so that the power consumption is alsoincreased.

[0010] In order to solve the conventional drawback described above, afollowing conventional method is used.

[0011] In the circuit operable under a low voltage shown in FIG. 1, whenthe two-input NAND gate 1 operates, the level of the control signal(CSB1) 9 is set to a low level and the control signal (CS1) 11, which isan inverted signal of the control signal (CSB1) 9 in voltage level, isset to a high level. Thereby, both the p channel MOS FET 8 and the nchannel MOS FET 10 are ON and the voltage potential of the hypotheticalpower source line 12 rises up to the voltage level of the power sourceand the voltage potential of the ground line 13 is fallen to the voltagelevel of the ground GND 7. As a result, two-input NAND gate 1 operatesas a normal NAND gate. In this case, because the threshold voltage ofeach of the MOS FETs 2 to 5 is set to the low value, it is possible tooperate the two-input NAND gate 1 at a high speed when the voltage levelof the power source 6 is low.

[0012] When the two-input NAND gate 1 is not used, the control signal(CSB1) 9 is set to the high level and the control signal (CS1) 11, thatis the inverted signal of the control signal (CSB1) 9 in voltage level,is set to the low level. At this time, both the p channel MOS FET 8 andthe n channel MOS FET 10 become OFF, so that the hypothetical powersource lines 12 and the hypothetical ground line 13 are electricallydisconnected from the power source 6 and the ground 7, respectively.

[0013] Because it is so formed that the absolute value of the thresholdvoltage of each of the p channel MOS FET 8 and the n channel MOS FET 10is higher than that of each of the MOS FETs 2 to 5, it is possible tosuppress the value of the leak current within a lower value.

[0014] In general, in a region in which the voltage between the gate andthe source of a MOS FET is lower than a threshold voltage of the MOSFET, the magnitude of the leak current flowing through the source andthe drain is exponentially increased according to the value of thevoltage of the gate. It is therefore possible to greatly reduce the leakcurrent when the MOS FETs 2 to 5 and the MOS FETs 8 and 10 havedifferent threshold voltage values.

[0015] Although the above conventional example shows the two-input NANDgate 1 comprising MOS FETs, each having the lower absolute value of thethreshold voltage, it is possible to apply the above method to manykinds of semiconductor integrated circuits in size and function such asother logical circuits, memory devices, and the like.

[0016]FIG. 2 is the conventional layout of the circuit comprising gatearrays capable of performing under a low voltage as the semiconductorintegrated circuit shown in FIG. 1. In FIG. 1, both the p channel MOSFET 8 and the n channel MOS FET 10, each having a higher thresholdvoltage, are formed in regions 260, and the p channel MOS FETs 2 and 3and the n channel MOS FETs 4 and 5, each having a lower thresholdvoltage, are formed in regions 270 that are the regions other than theregion 260 in the array section 210. Further, the electric power fromthe power source 6, the ground voltage from the ground 7, and thecontrol signals 9 and 11 are supplied to the array section 210 throughinput/output circuit regions 220, 230, 240, and 250.

[0017] Because the conventional circuit capable of performing under thelow voltage as the semiconductor integrated circuit device has theconfiguration described above, namely, because both MOS FETs having thehigh threshold voltage and the low threshold voltage are formed in thearray section 210, it is difficult to use the regions 260 (that is usedfor the MOS FETs having the high threshold voltage) in the array sectionfor the internal circuits such as the two-input NAND gate 1 and wiringtransferring signals and voltages of power source. Thereby, it becomesto reduce the wiring efficiency in the array section 210 and theperipheral section thereof. This limitation causes to reduce the densityof the layout of the semiconductor integrated circuit device.

[0018] In addition, in order to obtain a low power consumption, when theMT CMOS is used in a previously designed circuit (or in a pre-designedcircuit) in which the MT CMOS is not used, it is difficult to use thepre-designed circuit without changing this layout pattern by thelimitation of the regions 260 in the array section 210 in which the MOSFETs having the high threshold voltage are formed. This conventionallayout of the circuit causes a drawback that it must be required todesign a new layout pattern again.

SUMMARY OF THE INVENTION

[0019] Accordingly, an object of the present invention is, with dueconsideration to the drawbacks of the conventional semiconductorintegrated circuit device, to provide a semiconductor integrated circuitdevice as a circuit capable of performing under a lower voltage byforming MOS FTEs having a higher threshold voltage in regions other thanthe array section, capable of improving a layout efficiency and capableof using pre-designed circuits to be used in an array section withoutany changing of its circuit design and layout pattern.

[0020] In accordance with a preferred embodiment of the presentinvention, a semiconductor integrated circuit device comprises an arraysection in which a plurality of low threshold voltage metal oxidesemiconductor field effect transistors (MOS FETS) are formed in arrayform, and input/output circuit forming areas other than the arraysection in which high threshold voltage MOS FETs having a high thresholdvoltage are formed. In the semiconductor integrated circuit devicedescribed above, the threshold voltage of each of the high thresholdvoltage MOS FETs is higher than a threshold voltage of each of theplurality of low threshold voltage MOS FETs formed in said arraysection.

[0021] In accordance with another preferred embodiment of the presentinvention, a semiconductor integrated circuit device comprises an arraysection in which a plurality of low thr shold voltage metal oxidesemiconductor field effect transistors (MOS FETs) are formed in arrayform, and input/output circuit forming areas located at peripheralsections of the array section, each area comprising a first area inwhich input/output circuits are formed and a second area in which MOSFETs whose absolute vale of a threshold voltage being higher than anabsolute value of a threshold voltage value of each of the plurality oflow threshold voltage MOS FETs formed in the array section.

[0022] In accordance with another preferred embodiment of the presentinvention, a semiconductor integrated circuit device comprises an arraysection in which a plurality of metal oxide semiconductor field effecttransistors (MOS FETs) are formed in array form, and a plurality ofareas, located at peripheral sections of the array section, in whichhigh threshold voltage metal oxide field effect transistors (MOS FETs)and low threshold voltage MOS FETs are formed. In the semiconductorintegrated circuit device described above, an absolute value of athreshold voltage of each of the high threshold voltage MOS FETs ishigher than an absolute vale of a threshold voltage of each of theplurality of MOS FETs formed in the array section, and an absolute valueof a threshold voltage of each of the low threshold voltage MOS FETs islower than the absolute vale of the threshold voltage of each of thehigh threshold voltage MOS FETs, and each of the plurality of areas hasan input/output circuit forming area having a same configuration.

[0023] In the semiconductor integrated circuit device as anotherpreferred embodiment of the present invention, the plurality of highthreshold voltage MOS FETs are formed at areas of four corners otherthan the array section and the input/output circuit forming sections inthe semiconductor integrated circuit.

[0024] In the semiconductor integrated circuit device as anotherpreferred embodiment of the present invention, the plurality of highthreshold voltage MOS FETs are formed at space areas between the arraysection and the input/output circuit forming sections in thesemiconductor integrated circuit.

[0025] In the semiconductor integrated circuit device as anotherpreferred embodiment of the present invention, switch circuits forsupplying power sources to the array section and electrically cuttingthe power sources from the array section are formed in the input/outputcircuit forming areas by using the high threshold voltage MOS FETs, andinput/output circuits for inputting signals to the array section andoutputting the signals from the array section are formed in theinput/output circuit forming areas by using both the high thresholdvoltage MOS FETs and the low threshold voltage MOS FETs.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] These and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings, in which:

[0027]FIG. 1 is a circuit diagram showing a low voltage circuit capableof performing under a low voltage as a semiconductor integrated circuitdevice of the first embodiment according to the present invention;

[0028]FIG. 2 is a diagram showing a layout pattern of a conventionalsemiconductor integrated circuit device corresponding to the low voltagecircuit capable of performing under the low voltage shown in FIG. 1;

[0029]FIG. 3 is a diagram showing a layout pattern of regions in whichthe low voltage circuits capable of performing under the low voltageshown in FIG. 1 are formed as the semiconductor integrated circuitdevice of the first embodiment according to the present invention;

[0030]FIG. 4 is a diagram showing detailed layout patterns of theregions in which input/output circuits are formed in the semiconductorintegrated circuit as the first embodiment shown in FIG. 3;

[0031]FIG. 5 is a detailed circuit diagram showing the input/outputcircuit formed in the input/output forming region in the semiconductorintegrated circuit of the first embodiment shown in FIG. 3;

[0032]FIG. 6 is a diagram showing another layout pattern of the lowvoltage circuit capable of performing under the low voltage as thesemiconductor integrated circuit device of the second embodimentaccording to the present invention;

[0033]FIG. 7 is a diagram showing another layout pattern of the regionsin which the input/output circuits are formed in the semiconductorintegrated circuit as the second embodiment shown in FIG. 6;

[0034]FIG. 8 is a diagram showing another layout pattern of the lowvoltage circuit capable of performing under the low voltage as thesemiconductor integrated circuit device of the third embodimentaccording to the present invention; and

[0035]FIG. 9 is a diagram showing another layout pattern of the lowvoltage circuit capable of performing under the low voltage as thesemiconductor integrated circuit device of the fourth embodimentaccording to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] Other features of this invention will become apparent through thefollowing description of preferred embodiments which are given forillustration of the invention and are not intended to be limitingthereof.

[0037] Preferred embodiments of the semiconductor integrated circuitdevice according to the present invention will now be described withreference to the drawings.

[0038] First Embodiment

[0039]FIG. 1 is the circuit diagram showing the circuit capable ofperforming under the low voltage as the semiconductor integrated circuitdevice of the first embodiment according to the present invention.

[0040] The circuit capable of performing under the low voltage(hereinafter referred to as the low voltage operation circuit) comprisesmulti-threshold complementary metal oxide semiconductors (hereinafterreferred to as MT CMOS). In FIG. 1, the reference number 1 designates atwo-input NAND gate, each of the reference numbers 2 and 3 denotes a pchannel type metal oxide semiconductor field effect transistor(hereinafter referred to as a p MOS FET). Each of the reference numbers4 and 5 indicates a n channel type metal oxide semiconductor fieldeffect transistors (hereinafter referred to as a n channel MOS FET). Theabsolute value of the threshold voltage of this p MOS FET is set to alow value and the absolute value of the threshold voltage of this n MOSFET is set to a high value. The reference number 6 designates the powersource, 7 denotes the ground power source. The reference number 8indicates the p channel MOS FET connected between the power source 6 anda power source line 12 as a hypothetical power source line. This pchannel MOS FET 8 becomes active when a gate terminal of the P channelMOS FET 8 receives the control signal 9. The reference number 10indicates the n channel MOS FET connected between the ground powersource 7 and the ground voltage line 13 that is a hypothetical groundline. This n channel MOS FET 10 becomes active when a gate terminal ofthe n channel MOS FET 10 receives the control signal 11. In this circuitshown in FIG. 1, it is formed so that the values of the thresholdvoltages of the p channel MOS FET 8 and the n channel MOS FET 10 arehigher than the values of the threshold voltages of the p channel MOSFETs 2 and 3 and the n channel MOS FETs 4 and 5 forming the two-inputNAND gate 1, respectively.

[0041]FIG. 3 is a diagram showing a layout pattern of the low voltageoperation circuit shown in FIG. 1 as the semiconductor integratedcircuit device of the first embodiment according to the presentinvention. In FIG. 1, the reference number 21 designates an arraysection in which a plurality of MOS FETs are arranged in array form, 22to 25 denote input/output circuit section in which input/output circuitsare formed in peripheral regions in the array section 21. The referencenumber 27 indicates regions in which MOS FETs (high threshold voltageMOS FET) are formed in and each MOS FET in the regions 27 has a higherthreshold voltage than the threshold voltage of each MOS FET formed inthe array section 21. In the regions other than the regions 27 in theinput/output circuit sections 22 to 25, input/output circuits areformed.

[0042]FIG. 4 is a diagram showing detailed layout patterns of theregions in which input/output circuits are formed in the semiconductorintegrated circuit as the first embodiment shown in FIG. 3. In FIG. 4,the reference numbers 28 and 30 designate signal pads, 29 indicates apower source pad, and 31 to 33 denote lines as wiring connecting thesignal pads 28 and 30 and the power source pad 29 to the input/outputcircuits formed in the regions 34 and 35 and switch circuits formed inthe region 7. In this case shown in FIG. 4, the input/output circuitsare formed in the regions 34 and 35 (namely, those regions 34 and 35correspond to the regions other than the region 27 in the input/outputforming regions 22 to 25 shown in FIG. 3) in which the low thresholdvoltage MOS FETs are formed, and the switch circuits are formed in theregion 27 in which the high threshold voltage MOS FET are formed.

[0043] Further, FIG. 5 is a detailed circuit diagram showing theinput/output circuit formed in the input/output forming region in thesemiconductor integrated circuit of the first embodiment shown in FIG.3. In FIG. 5, the reference number 36 designates an output buffercircuit, 37 denotes an input buffer circuit. The reference number 38designates an output signal generated by internal circuits such as thetwo-input NAND gate 1 and the like, 0.39 indicates a control signal bywhich the output buffer circuit 36 enters the active state or theinactive state. The reference number 40 indicates an input signal to betransferred to the internal circuits, 41 designates an input/outputsignal transferred to the signal pads 28 and 30.

[0044] Next, a description will be given of the operation of thesemiconductor integrated circuit device as the first embodiment.

[0045] In the low voltage operation circuit shown in FIG. 1, when thetwo-input NAND gate 1 operates, the level of the control signal 9 is setto the low level, and the level of the control signal that is theinverted level of the control signal 9 is set to the high level.Thereby, both the p channel MOS FET 8 and the n channel MOS FET 10 areON and the level of the hypothetical power source line 12 is risen up tothe voltage level of the power source 6 and the level of thehypothetical ground line 13 is fallen into the voltage level of theground 7. As a result, the two-input NAND gate 1 performs the normaloperation. In this case, because the value of the threshold voltage ofeach of the MOS FETs 2 to 5 is set to a low value, it is possible tooperate the semiconductor integrated circuit of the first embodiment ata high speed even if the voltage level of the power source 6 is a low.

[0046] When the two-input NAND gate 1 is not used, the level of thecontrol signal 9 is set to the high level and the level of the controlsignal 11 is set to the low level. In this case, both the p channel MOSFET 8 and the n channel MOS FET 10 become OFF. Thereby, both thehypothetical power source line 12 and the hypothetical ground line 13are disconnected electrically from the power source 6 and the ground 7.Because both the absolute value of the threshold voltage of each of thep channel MOS FET 8 and the n channel MOS FET 10 is set to the highvalue rather than that of each of the MOS FETs 2 to 5, it is possible tosuppress the magnitude of the leak current as small as possible.

[0047] In general, in the region in which MOS FETs (in each MOS FET, avoltage between the gate and the source of this MOS FET is a lower valuethan the threshold voltage of this MOS FET) are formed, because the leakcurrent flowing through the source and the drain is increasedexponentially corresponding to the increasing of the gate voltage, it ispossible to reduce the leak current when the two-input NAND gate 1 isnot used by setting the different threshold voltages to the MOS FETs 2to 5 and the MOS FETs 8 and 10.

[0048] In the explanation of the semiconductor integrated circuit deviceof the first embodiment described above, although the two-input NANDgate 1 is used as the circuit comprising MOS FETs having the lowthreshold voltage, it is possible to apply this concept of the presentinvention to other kinds of circuits having different hardware sizes toform other logical devices, memory devices, and semiconductor integratedcircuit devices.

[0049]FIG. 3 is the layout pattern of the low voltage operating circuitshown in FIG. 1 comprising gate arrays. In FIG. 3, the p channel MOS FET8 and the n channel MOS FET 10 having the higher threshold voltageforming the switching circuits are formed in the region 27, and the pchannel MOS FETS 2 and 3 and the n channel MOS FETs 4 and 5 having thelower threshold voltage forming the two-input NAND gate 1 are formed inthe array section 21.

[0050] The voltages of the power source 6 and the ground 7, and thecontrol signals 9 and 11 are provided to/from the array section 21through the regions 22 to 25 in which the input/output circuits areformed.

[0051]FIG. 4 is the diagram showing the layout pattern of the switchcircuits and the input/output circuits formed in the input/outputcircuit forming regions 22 to 25.

[0052] In general, the semiconductor integrated circuit device has thesignal pads and the power source pads. Through the signal pads, variouskinds of signals are transferred between the internal circuits andexternal circuits. The voltage and the ground voltage are provided tothe internal circuits of the semiconductor integrated circuit devicethrough the power source pads. In addition, the input/output circuitregions corresponding to the input/output pads are used for forming theinput/output circuits. On the contrary, the input/output circuit regionscorresponding to the power source pads are only used for connecting thepower source lines and are not used for forming the input/outputcircuits comprising MOS FETs. Therefore it is possible to form the MOSFETs having a high threshold voltage in those input/output circuitregions corresponding to the power source pads.

[0053] In FIG. 4, the MOS FETs having the high threshold voltage areformed in the region corresponding to the power source pad 29. In thisregion, the p channel MOS FET 8 and the n channel MOS FET 10 having thehigh threshold voltage as the switch circuits are formed. Theinput/output circuit regions corresponding to the signal pads 28 and 30are the regions 34 and 35 in which the MOS FETs having the low thresholdvoltage are formed. In those regions 34 and 35, the input/outputcircuits are formed.

[0054]FIG. 5 is the detailed circuit diagram showing the input/outputcircuit shown in FIG. 4. when the signals from the semiconductorintegrated circuit are transferred to other circuits, when receiving thecontrol signal 39, the output buffer circuit 36 is activated, andthereby, the output signal 38 is amplified by the MOS FET having alarger area formed in the output buffer 36 and transferred to theexternal devices, that are located in outside areas of the semiconductorintegrated circuit device, as the input/output signal 41 having a largerdriving ability.

[0055] Next, when an external signal generated by the outside devices ofthe semiconductor integrated circuit device is transferred to theinternal circuits in the semiconductor integrated circuit device, theoutput buffer 36 receives the control signal 39, so that the outputbuffer 39 becomes inactive. Thereby, both two lines connected to theoutput buffer 36 are disconnected electrically. Therefore, theinput/output signal 41 is amplified by the input buffer 40 without anyinfluence from the output signal 38. Then, the input/output signal 41amplified by the input buffer 37 is transferred to the internal circuitin the semiconductor integrated circuit device. In the semiconductorintegrated circuit device as the first embodiment, both the outputbuffer circuit 36 and the input buffer circuit 37 are formed by usingthe MOS FETs having the low threshold voltage.

[0056] As described above, according to the semiconductor integratedcircuit device as the first embodiment, it is possible to realize thesemiconductor integrated circuit device including MT CMOSs capable ofperforming at a high speed and of achieving a low power consumption. Inaddition to this effect of the present invention, it may prevent todecrease the density of the layout pattern of the semiconductorintegrated circuit device. On the contrary, the conventionalsemiconductor integrated circuit device shown in FIG. 2 has a lowerdensity in the layout pattern because the region 260, in which the MOSFETs having the high threshold voltage are formed, limits the increasingof the density of the layout pattern.

[0057] Further, according to the first embodiment of the presentinvention, it is possible to use the pre-designed layout pattern inwhich no MT CMOS is used, it is possible to perform the wiring designefficiently. Furthermore, because the p channel MOS FET 8 and the nchannel MOS FET 10 having the high threshold voltage are formed in theregions 27 in the input/output circuit forming regions 22 to 25, it ispossible to use the pre-designed layout pattern of the input/outputcircuit forming regions 22 to 25 without any changing of the layoutpattern. Thereby, it is possible to perform the layout design and thewiring design efficiently, and to reduce the design cost for thesemiconductor integrated circuit device.

[0058] Second Embodiment

[0059]FIG. 6 is a diagram showing another layout pattern of the lowvoltage circuit capable of performing under the low voltage as thesemiconductor integrated circuit device of the second embodimentaccording to the present invention. In FIG. 6, each of the input/outputcircuit forming regions 221, 231, 241, and 251 is made up of a pluralityof regions. In each of the regions 221, 231, 241, and 251, both MOS FETshaving a low threshold voltage (hereinafter, also referred to as lowthreshold voltage MOS FET) and MOS FETs having a high threshold voltage(hereinafter, also referred to as high threshold voltage MOS FET) areformed. Each of the regions 221, 231, 241, and 251 is the sameconfiguration in the semiconductor integrated circuit as the secondembodiment. The reference numbers 51 to 54 designate regions in theregions 221, 231, 241, and 251 in which the high threshold voltage MOSFETs are formed. In FIG. 6, the regions 51 to 54 are designated byshadowed lines or slanted lines.

[0060]FIG. 7 is a diagram showing a layout pattern of the regions 221,231, 241, and 251 in which the input/output circuits comprising MOS FETsare formed in the semiconductor integrated circuit as the secondembodiment shown in FIG. 6. In FIG. 7, the reference numbers 55 to 57designate the regions in which the high threshold voltage MOS FETs areformed, and the reference numbers 58 to 60 designate the regions inwhich the low threshold voltage MOS FETs are formed. In FIG. 7, theregions 55, 56, and 57 are designated by shadowed lines or slantedlines. The reference numbers 61 and 63 designate input/output circuitslocated between the regions 55 for forming the high threshold voltageMOS FETs and the region 58 for forming the low threshold voltage MOSFETs, and between the regions 57 for forming the high threshold voltageMOS FETs and the region 60 for forming the low threshold voltage MOSFETs. Each of the regions in which the input/output circuits 61 and 63are formed has the same configuration. The reference number 62 indicatesa switch circuit located in the region 56 in which the high thresholdvoltage MOS FETs are formed.

[0061] Next, a description will be given of the operation of the lowvoltage circuit capable of performing under a low voltage as thesemiconductor integrated circuit device as the second embodiment.

[0062] In the input/output circuit forming regions 221, 231, 241, and251 in the semiconductor integrated circuit device as the secondembodiment, shown in FIG. 6, both the high threshold voltage MOS FETsand the low threshold voltage MOS FETs may be used. In general, theinput/output circuit comprises MOS FETs having a larger size in area inorder to drive external devices as heavy load devices. When thisinput/output circuit comprises MOS FET having a low threshold voltage, alarge leak current flows. This causes to increase the power consumptionof semiconductor integrated circuit device.

[0063] As shown in FIG. 7, according to the semiconductor integratedcircuit device as the second embodiment, it is possible to halt flowingof the leak current because the input/output circuits 61 and 63 may beformed in both the high threshold MOS FET forming region 55 and the lowthreshold MOS FET forming region 58, and the high threshold MOS FETforming region 57 and the low threshold MOS FET forming region 60,respectively.

[0064] For example, it is possible to cut the flow of the leak currentbecause the output buffer circuit 36 in the input/output circuit shownin FIG. 5 may comprises the high threshold voltage MOS FETs formed inthe high threshold voltage MOS FET forming region 55.

[0065] In addition, the switch circuit 62 shown in FIG. 7 comprises thep channel MOS FET 8 and the n channel MOS FET 10 shown in FIG. 1 thatare made up of only the high threshold voltage MOS FETs formed in theregion 62.

[0066] As described above, according to the semiconductor integratedcircuit device as the second embodiment, it is possible to obtain thesame effect of the first embodiment of the present invention. Inaddition to this effect, because it is possible to form all of the gatesof the input/output circuits, it is possible to form the switch circuitsfor the power source pads and the input/output circuits for the signalpads at optional positions. This causes to form circuits having optionalfunctions by using gate arrays. Furthermore, because it is possible toform the input/output circuits by using both the high threshold voltageMOS FETs and the low threshold voltage MOS FETs, it is possible to formthe input/output circuits in which a small value of a leak currentflows. Therefore this causes to decrease the power consumption of thesemiconductor integrated circuit device.

[0067] Third Embodiment

[0068]FIG. 8 is a diagram showing another layout pattern of the lowvoltage circuit capable of performing under the low voltage as thesemiconductor integrated circuit device as the third embodimentaccording to the present invention. In FIG. 8, the reference numbers 71,72, 73, and 74 designate space areas located at four corners of thearray section 21 other than the input/output circuit forming regions 22,23, 24, and 25 in a semiconductor chip. In this third embodiment, thehigh threshold voltage MOS FETs are formed at the space areas 71 to 74in the four corners. In FIG. 8, the space areas 55, 56, and 57 aredesignated by shadowed lines or slanted lines.

[0069] Next, a description will be given of the operation of thesemiconductor integrated circuit device as the third embodiment.

[0070] In general, MOS FETs are not formed at the space areas 71 to 74located at the four corners in a conventional semiconductor chip. In thethird embodiment, the p channel MOS FET 8 and the n channel MOS FET 10are formed in the space areas 71 to 74 in the four corners by using MOSFETs of the high threshold voltage.

[0071] As described above, according to the semiconductor integratedcircuit device as the third embodiment, it is possible to obtain thesame effect of the semiconductor integrated circuit device as the firstembodiment. In addition to this effect, because it is possible to formthe gates having the same configuration in the input/output circuitforming regions 22 to 25 in the semiconductor integrated circuit as thethird embodiment, it is possible to form the input/output circuits forthe signal pads at desired areas and possible to form desired circuitsby using gate arrays.

[0072] Fourth Embodiment

[0073]FIG. 9 is a diagram showing another layout pattern of the lowvoltage circuit capable of performing under the low voltage as thesemiconductor integrated circuit device of the fourth embodimentaccording to the present invention. In FIG. 9, the reference number 75designates a space area located between the array section 21 and theinput/output circuit forming areas 22 to 25. In FIG. 9, the space area71 is designated by shadowed lines or slanted lines. In the space area75, the MOS FETs having the high threshold voltage are formed.

[0074] Next, a description will be given of the operation of thesemiconductor integrated circuit device as the fourth embodiment.

[0075] In general, MOS FETs are not formed at the space area 75 locatedbetween the array section 21 and the input/output circuit formingsections 22 to 25 in the conventional semiconductor chip. In the fourthembodiment of the present invention, the p channel MOS FET 8 and the nchannel MOS FET 10 are formed in the space area 75 by using MOS FETs ofthe high threshold voltage.

[0076] As described above, according to the semiconductor integratedcircuit device as the fourth embodiment, it is possible to obtain thesame effect of the semiconductor integrated circuit device as the thirdembodiment. That is, it is possible to obtain the same effect of thesemiconductor integrated circuit device as the third embodiment. Inaddition to this effect, because it is possible to form the gates havingthe same configuration in the input/output circuit forming regions 22 to25 in the semiconductor integrated circuit as the fourth embodiment, itis possible to form the input/output circuits for the signal pads atdesired areas and possible to form desired circuits by using gatearrays.

[0077] As set fourth above, according to the semiconductor integratedcircuit device of the present invention, because only the low thresholdvoltage MOS FETs are formed in the array section, it is possible to havea higher density of the layout pattern of the semiconductor integratedcircuit device rather than that of the conventional semiconductorintegrated circuit device in which the limitation caused by the highthreshold voltage MOS FET arranged in the array section decreases thedensity of the layout pattern. In addition to this, it is possible touse the pre-designed layout pattern in which no MT CMOSs are usedwithout any changing of its design. It is thereby possible to performthe layout design and to perform the wiring efficiently.

[0078] In addition, according to the semiconductor integrated circuitdevice of the present invention, because the high threshold voltage MOSFETs are formed in areas, that are not used normally, other than theinput/output circuit forming areas, it is possible to use apply thelayout pattern, that has been designed for the input/output circuitforming regions, without any changing of its layout pattern. It isthereby possible to perform the layout design and to perform the wiringefficiently.

[0079] Furthermore, according to the semiconductor integrated circuitdevice of the present invention, because the all of the input/outputcircuit forming regions have the same configuration, it is possible toform the switch circuits and the input/output circuits at desiredpositions. Furthermore, because both the high and low threshold voltageMOS FETs are used before forming the input/output circuits, it ispossible to form the input/output circuits in which a smaller leakcurrent flows. Moreover, it is thereby possible to reduce the powerconsumption of the semiconductor integrated circuit.

[0080] Moreover, according to the semiconductor integrated circuitdevice of the present invention, because all of the input/output circuitforming regions have the same configuration, it is possible to form theinput/output circuits used for the signal pads at desired position inthe semiconductor chip, and possible to form an optional circuit byusing gate arrays.

[0081] Furthermore, according to the semiconductor integrated circuitdevice of the present invention, because the input/output circuits areformed by using both the high threshold voltage MOS FETs and the lowthreshold voltage MOS FETs, a small leak current flows in thoseinput/output circuits, it is possible to reduce the power consumption ofthe semiconductor integrated circuit.

[0082] While the above provides a full and complete disclosure of thepreferred embodiments of the present invention, various modifications,alternate constructions and equivalents may be employed withoutdeparting from the scope of the invention. Therefore the abovedescription and illustration should not be construed as limiting thescope of the invention, which is defined by the appended claims.

What is claimed is:
 1. A semiconductor integrated circuit device comprising: an internal circuit section in which an integrated circuit is formed, the integrated circuit including at least MOS transistors of same conductivity type, a plurality of terminal pads including signal pads, a plurality of buffer regions connected to said signal pads, respectively, each buffer region including at least one of an input buffer circuit and an output buffer circuit, the input buffer circuit connected between the internal circuit and one of the signal pads and transfers a signal from the one signal pad to the internal circuit, and the output buffer circuit connected between the internal circuit and the one signal pad and transfers a signal from the internal circuit to the one signal pad, and a space region defined by one corner of said internal circuit section, a first hypothetical line extends from a first side as a boundary of said internal circuit section from the one corner, and a second hypothetical line extends from a second side as a boundary of said internal circuit section from the one corner, said second hypothetical line being orthogonal with said first side at the one corner, wherein a MOS transistor, having a threshold voltage whose absolute value is higher than that of each of the MOS transistors in said internal circuit section, is formed in said space region.
 2. A semiconductor integrated circuit device comprising: an internal circuit section in which an integrated circuit is formed, the integrated circuit including at least MOS transistors of same conductivity type, a plurality of terminal pads including signal pads, a plurality of buffer circuits connected to said signal pads, respectively, each buffer circuit including at least one of an input buffer circuit and an output buffer circuit, the input buffer circuit connected between the internal circuit and one of the signal pads and transfers a signal from the one signal pad to the internal circuit, and the output buffer circuit connected between the internal circuit and the one signal pad and transfers a signal from the internal circuit to the one signal pad, and four space regions corresponding to four different corners of the internal circuit section, respectively, each space region defined by one corner of the four, a first hypothetical line extends from a first side as a boundary of said internal circuit section from the one corner, and a second hypothetical line extends from a second side as a boundary of said internal circuit section from the one corner, said second hypothetical line being orthogonal with said first side at the one corner, wherein a MOS transistor, having a threshold voltage whose absolute value is higher than that of each of the MOS transistors in said internal circuit section, is formed in each space region.
 3. The semiconductor integrated circuit device according to claim 1, wherein the MOS transistor formed at the one space region is a switch which supplies an electrical power to the internal circuit from a power source pad.
 4. The semiconductor integrated circuit device according to claim 2, wherein the MOS transistor formed at each space region is a switch which supplies an electrical power to the internal circuit from a power source pad.
 5. A semiconductor integrated circuit device comprising: an internal circuit section in which an integrated circuit is formed, the integrated circuit including at least MOS transistors of same conductivity type, a plurality of input/output circuit regions arranged opposite to four sides of said internal circuit section, respectively, each input/output circuit region including a plurality of buffer circuits connected to the signal pads, respectively, each buffer circuit including at least one of an input buffer circuit and an output buffer circuit, the input buffer circuit connected between the internal circuit and one of the signal pads and transfers a signal from the one signal pad to the internal circuit, and the output buffer circuit connected between the internal circuit and the one signal pad and transfers a signal from the internal circuit to the one signal pad; and MOS transistors having threshold voltages whose absolute values are higher than that of each of the MOS transistors in said internal circuit section, and arranged between said internal circuit section and said plurality of input/output circuit regions and in a loop surrounding said internal circuit section.
 6. The semiconductor integrated circuit device according to claim 5, wherein the MOS transistor formed in the space region is a switch which supplies an electrical power to the internal circuit from a power source pad. 